HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 108
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 2 CPU
2.9
2.9.1
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate
the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,
special care is necessary to use these instructions for the registers and the ports that include write-
only bit.
The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.
Rev. 3.00 Mar 17, 2006 page 56 of 926
REJ09B0283-0300
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 22, Power-Down Modes.
Usage Note
Usage Notes on Bit-wise Operation Instructions
A transition can also be made to the reset state when the watchdog timer overflows.
Bus-released state
handling state
Reset state *
Exception
Reset state
RES = High
1
Figure 2.13 State Transitions
External interrupt request
Program execution state
End of bus request
STBY = High,
RES = Low
Bus request
Hardware standby
Software standby
Power down state *
Sleep mode
mode *
mode
2
3
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