HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 254
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
6.7.5
When the DCTL pin is fixed to 1, synchronous clock (SDRAM ) is output from the CS5 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to 1 or 2,
SDRAM is 90° phase shift from . Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between
and SDRAM . When the frequency multiplication factor of the PLL circuit is 4, the phase of
SDRAM and that of are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAM of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to 1 or 2.
Note: SDRAM output timing is shown when the frequency multiplication factor of the PLL
6.7.6
The four states of the basic timing consist of one T
output cycle) state, and the T
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
Rev. 3.00 Mar 17, 2006 page 202 of 926
REJ09B0283-0300
Figure 6.43 Relationship between and SDRAM (when PLL frequency multiplication
circuit is 1 or 2.
Synchronous DRAM Clock
Basic Operation Timing
SDRAMø
c1
and two T
factor is 1 or 2)
c2
(column address output cycle) states.
T cyc
p
(precharge cycle) state, one T
1/4 T cyc (90˚)
r
(row address
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