HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 432
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 8 EXDMA Controller
8.4.11
Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in
EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-
cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the
next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 8.28 to 8.30 show operation timing examples for various conditions.
Rev. 3.00 Mar 17, 2006 page 380 of 926
REJ09B0283-0300
Bus cycle
CPU
operation
ETEND
EDA bit
pin
Examples of Operation Timing in Each Mode
EDA = 1
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
write
0
Bus release
Internal bus space
1
3 cycles
cycles
(No Contention/Dual Address Mode)
EXDMA
read
EXDMA
write
1 cycle
Bus
release
EXDMA
read
EXDMA
write
Bus
release
EXDMA
Last transfer cycle
read
EXDMA
write
0
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