HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 247
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus
controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is
connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be
cleared to 0 in MSTPCRH.
6.6.13
When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
Address bus
RASn (CSn)
UCAS, LCAS
OE (RD)
WR (HWR)
Data bus
Note: n = 2 to 5
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
Software
standby
T
rc3
by 2 States
T
rp1
T
rp2
Rev. 3.00 Mar 17, 2006 page 195 of 926
T
p
Section 6 Bus Controller (BSC)
DRAM space write
T
r
T
REJ09B0283-0300
c1
T
c2
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