HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 361

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
7.5.8
Basic Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
CPU cycle
DMAC cycle (1-word transfer)
CPU cycle
T
T
T
T
T
T
T
T
1
2
1
2
3
1
2
3
Source
Destination address
address
Address bus
RD
HWR
LWR
Figure 7.17 Example of DMA Transfer Bus Timing
Rev. 3.00 Mar 17, 2006 page 309 of 926
REJ09B0283-0300