HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 133

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The interrupt exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Legend:
1:
0:
—: Retains value prior to execution.
(EXR) are saved in the stack.
from the vector table to the PC, and program execution starts from that address.
(EXR) are saved in the stack.
from the vector table to the PC, and program execution starts from that address.
Set to 1
Cleared to 0
Interrupt Control Mode
Trap Instruction
Status of CCR and EXR after Trap Instruction Exception Handling
0
2
1
1
I
CCR
UI
—
—
Rev. 3.00 Mar 17, 2006 page 81 of 926
Section 4 Exception Handling
I2 to I0
—
—
REJ09B0283-0300
EXR
—
T
0