HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 848

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 19 Flash Memory (F-ZTAT Version)
19.8.1
When programming data or programs to the flash memory, the program/program-verify flowchart
shown in figure 19.10 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be programmed to the flash memory without subjecting
the chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128-
4. Consecutively transfer 128 bytes of data in byte units from the programming data area,
5. The time during which the P bit is set to 1 is the programming time. Figure 19.10 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
8. The maximum number of repetitions of the program/program-verify sequence to the same bit
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REJ09B0283-0300
programming has already been performed.
performed even if programming fewer than 128 bytes. In this case, H'FF data must be written
to the extra addresses.
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 19.10.
reprogramming data area, or additional-programming data area to the flash memory. The
program address and 128-byte data are latched in the flash memory. The lower 8 bits of the
start address in the flash memory destination area must be H'00 or H'80.
allowable programming times.
Set a value greater than (y + z2 +
are B'00. Verify data can be read in words from the address to which a dummy write was
performed.
(N) must not be exceeded.
Program/Program-Verify
+ ) µs as the WDT overflow period.