HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 326
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 7 DMA Controller (DMAC)
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 17, 2006 page 274 of 926
REJ09B0283-0300
DMABCRL
Bit Name
DTE1B
DTE1A
DTE0B
DTE0A
DTIE1B
DTIE1A
DTIE0B
DTIE0A
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Data Transfer Enable 1B
Data Transfer Enable 1A
Data Transfer Enable 0B
Data Transfer Enable 0A
If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source selected by the DTF3 to DTF0 bits in
DMACR. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
[Setting condition]
When 1 is written to the DTE bit after reading
DTE = 0
Data Transfer End Interrupt Enable 1B
Data Transfer End Interrupt Enable 1A
Data Transfer End Interrupt Enable 0B
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit
is set to 1 when DTE = 0, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE bit to 1.
When initialization is performed
When the specified number of transfers
have been completed in a transfer mode
other than repeat mode
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
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