HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 212
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
6.5.2
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3
Area
8-bit access
space
16-bit access
space
Notes: Hi-Z: High-impedance state
6.5.3
8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Rev. 3.00 Mar 17, 2006 page 160 of 926
REJ09B0283-0300
Invalid: Input state; input value is ignored.
Valid Strobes
Basic Operation Timing
Data Buses Used and Valid Strobes
Access
Size
Byte
Byte
Word
Read/
Write
Read
Write
Read
Write
Read
Write
Address
—
—
Even
Odd
Even
Odd
—
—
Valid
Strobe
RD
HWR
RD
HWR
LWR
RD
HWR, LWR
Upper Data Bus
(D15 to D8)
Valid
Valid
Invalid
Valid
Hi-Z
Valid
Valid
Lower Data Bus
(D7 to D0)
Invalid
Hi-Z
Valid
Hi-Z
Valid
Valid
Valid
Invalid
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