HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 191

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit
12
11
10
9
8
Bit Name
CAST
—
RMTS2
RMTS1
RMTS0
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Column Address Output Cycle Number Select
Selects whether the column address output
cycle in DRAM access comprises 3 states or 2
states. The setting of this bit applies to all areas
designated as DRAM space.
0: 2 states
1: 3 states
Reserved
This bit can be read from or written to.
However, the write value should always be 0.
DRAM/Continuous Synchronous DRAM Space
Select
These bits designate DRAM/continuous
synchronous DRAM space for areas 2 to 5.
When continuous DRAM space is set, it is
possible to connect large-capacity DRAM
exceeding 2 Mbytes per area. In this case, the
RAS signal is output from the CS2 pin.
When continuous synchronous DRAM space is
set, it is possible to connect large-capacity
synchronous DRAM exceeding 2 Mbytes per
area. In this case, the RAS, CAS, and WE
signals are output from CS2, CS3, and CS4
pins, respectively. When synchronous DRAM
mode is set, the mode registers of the
synchronous DRAM can be set.
000: Normal space
001: Normal space in areas 3 to 5
010: Normal space in areas 4 and 5
011: DRAM space in areas 2 to 5
100: Continuous synchronous DRAM space
101: Synchronous DRAM mode setting (setting
110: Setting prohibited
111: Continuous DRAM space in areas 2 to 5
DRAM space in area 2
DRAM space in areas 2 and 3
(setting prohibited in the H8S/2678 Group)
prohibited in the H8S/2678 Group)
Rev. 3.00 Mar 17, 2006 page 139 of 926
Section 6 Bus Controller (BSC)
REJ09B0283-0300