HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 340

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
7.4.3
Auto-request is activated by register setting only, and transfer continues to the end. With auto-
request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
7.5
7.5.1
Table 7.4 lists the DMAC transfer modes.
Table 7.4
Transfer Mode
Short
address
mode
Rev. 3.00 Mar 17, 2006 page 288 of 926
REJ09B0283-0300
Activation by Auto-Request
Operation
Transfer Modes
Dual address mode
(1) Sequential mode
• Memory address incremented or
• Number of transfers:
(2) Idle mode
• Memory address fixed
• Number of transfers:
(3) Repeat mode
• Memory address incremented or
• Continues transfer after sending
Single address mode
• 1-byte or 1-word transfer for a single
• 1-bus cycle transfer by means of
• Sequential mode, idle mode, or
decremented by 1 or 2
1 to 65,536
1 to 65,536
decremented by 1 or 2
number of transfers (1 to 256) and
restoring the initial value
transfer request
DACK pin instead of using address
for specifying I/O
repeat mode can be specified
DMAC Transfer Modes
Transfer Source
• TPU channel 0 to 5
• SCI transmission complete
• SCI reception complete
• A/D converter conversion
• External request
• External request
compare match/input
capture A interrupt
interrupt
interrupt
end interrupt
Remarks
• Up to 4 channels can
• External request
• Single address mode
operate independently
applies to channel B
only
applies to channel B
only