HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 411

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 8.4.6, Repeat Area Function, for details.
Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA
Transfer, for details.
Figure 8.8 shows an example of DMA transfer timing in block transfer mode.
8.4.6
The EXDMAC has a function for designating a repeat area for source addresses and/or destination
addresses. When a repeat area is designated, the address register values repeat within the range
specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is
required to restore the address register value to the buffer start address each time the address
register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if
the repeat area function is used, the operation that restores the address register value to the buffer
start address is performed automatically within the EXDMAC.
The repeat area function can be set independently for the source address register and the
destination address register.
Transfer conditions:
• Single address mode
• BGUP = 0
• Block size (EDTCR[23:16]) = 3
EDREQ
EDRAK
Bus cycle
ETEND
Repeat Area Function
CPU
Figure 8.8 Example of Timing in Block Transfer Mode
CPU
CPU
EXDMAC
One-block transfer cycle
CPU cycle not generated
EXDMAC
Rev. 3.00 Mar 17, 2006 page 359 of 926
EXDMAC
Section 8 EXDMA Controller
REJ09B0283-0300
CPU