HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 430

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
EDREQ
EDREQ Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address
EDREQ
EDREQ
mode transfer activated by the EDREQ pin falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes
after the end of the single cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
Rev. 3.00 Mar 17, 2006 page 378 of 926
REJ09B0283-0300
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of .
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle.
Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held.
(As in [1], EDREQ pin low level is sampled at rise of , and request is held.)
EDREQ
Address bus
EDACK
DMA control
Channel
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
clearance period
Single
[3]
Request
Falling Edge
Transfer source/
DMA single
destination
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
clearance period
Single
[6]
Request
Transfer source/
DMA single Bus release
destination
Idle
Acceptance
resumed
[7]
EDREQ Pin
EDREQ
EDREQ