HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 93

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 2.4
Notes: 1. Size refers to the operand size.
Instruction
DIVXS
CMP
NEG
EXTU
EXTS
TAS *
MAC
CLRMAC
LDMAC
STMAC
2
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
B: Byte
W: Word
L: Longword
Arithmetic Operations Instructions (2)
Size *
B/W
B/W/L
B/W/L
W/L
W/L
B
—
—
L
1
Function
Performs signed division on data in two general registers:
either 16 bits ÷ 8 bits
32 bits ÷ 16 bits
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
Takes the two's complement (arithmetic complement) of data in a
general register.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
@ERd – 0, 1
Tests memory contents, and sets the most significant bit (bit 7) to 1.
(EAs)
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits
16 bits
0
Clears the multiply-accumulate register to zero.
Rs
Transfers data between a general register and a multiply-accumulate
register.
Rd ÷ Rs
0 – Rd
Rd (zero extension)
Rd (sign extension)
MAC
MAC, MAC
(EAd) + MAC
16 bits + 32 bits
16 bits + 42 bits
Rd
Rd
(<bit 7> of @ERd)
16-bit quotient and 16-bit remainder.
Rd
Rd
Rd
8-bit quotient and 8-bit remainder or
MAC
32 bits, saturating
42 bits, non-saturating
Rev. 3.00 Mar 17, 2006 page 41 of 926
REJ09B0283-0300
Section 2 CPU