HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 456

IC H8S MCU FLASH 256K 144-QFP

HD64F2676VFC33

Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2676VFC33

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 9 Data Transfer Controller (DTC)
Bit
0
Legend:
X: Don’t care
9.2.2
MRB selects the DTC operating mode.
Bit
7
6
5
4
to
0
Rev. 3.00 Mar 17, 2006 page 404 of 926
REJ09B0283-0300
Bit Name
Sz
Bit Name
CHNE
DISEL
CHNS
DTC Mode Register B (MRB)
Initial Value
Undefined
Initial Value
Undefined
Undefined
Undefined
Undefined
R/W
R/W
Description
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTCER
is not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.

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