HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 127

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.1
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
4.2
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Priority
High
Low
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
4. Trap instruction exception handling requests are accepted at all times in program
Exception Sources and Exception Vector Table
Exception Handling Types and Priority
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Type
Reset
Trace *
Direct transition *
Interrupt
Trap instruction *
Exception Types and Priority
1
Section 4 Exception Handling
4
2
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued. *
Started by execution of a trap instruction (TRAPA)
Rev. 3.00 Mar 17, 2006 page 75 of 926
Section 4 Exception Handling
REJ09B0283-0300
3