HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 299

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Note:
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
Previous Access
DRAM/continuous
synchronous DRAM *
space write
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
* In the H8S/2678 Group, the synchronous DRAM interface is not supported.
UCAS, LCAS
Note: n = 2 to 5
Address bus
RASn (CSn)
WE (HWR)
Next Access
Normal space read
DRAM/continuous
synchronous DRAM *
space read
Data bus
OE (RD)
Write Accesses to DRAM Space in RAS Down Mode
T
p
DRAM space read
ICIS2 *
0
1
0
1
T
r
T
c1
ICIS1
—
—
—
—
T
c2
Rev. 3.00 Mar 17, 2006 page 247 of 926
Idle cycle
ICIS0
—
—
—
—
DRAM space write
T
i
Section 6 Bus Controller (BSC)
DRMI
—
—
—
—
T
c1
T
c2
IDLC
—
0
1
—
0
1
REJ09B0283-0300
Idle cycle
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted