HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 475

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.7.3
By executing a second data transfer, and performing re-setting of the first data transfer, only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 9.12 shows the chain transfer when the
counter value is 0.
1. For the first transfer, set the normal mode for input data. Set fixed transfer source address
2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start
3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter
5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of
the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper 8 bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
an interrupt request is not sent to the CPU.
Chain Transfer when Counter = 0
Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 423 of 926
REJ09B0283-0300