HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 21

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.4
8.5
8.6
Section 9 Data Transfer Controller (DTC)
9.1
9.2
9.3
9.4
9.5
8.3.4
8.3.5
Operation .......................................................................................................................... 350
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 EXDMAC Bus Cycles (Single Address Mode) ................................................... 376
8.4.11 Examples of Operation Timing in Each Mode .................................................... 380
8.4.12 Ending DMA Transfer ......................................................................................... 393
8.4.13 Relationship between EXDMAC and Other Bus Masters ................................... 394
Interrupt Sources............................................................................................................... 395
Usage Notes ...................................................................................................................... 398
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
Features ............................................................................................................................. 401
Register Descriptions ........................................................................................................ 402
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
Activation Sources ............................................................................................................ 407
Location of Register Information and DTC Vector Table ................................................ 408
Operation .......................................................................................................................... 410
9.5.1
9.5.2
EXDMA Mode Control Register (EDMDR) ....................................................... 341
EXDMA Address Control Register (EDACR) .................................................... 346
Transfer Modes .................................................................................................... 350
Address Modes .................................................................................................... 351
DMA Transfer Requests ...................................................................................... 355
Bus Modes ........................................................................................................... 355
Transfer Modes .................................................................................................... 357
Repeat Area Function .......................................................................................... 359
Registers during DMA Transfer Operation.......................................................... 361
Channel Priority Order......................................................................................... 366
EXDMAC Bus Cycles (Dual Address Mode)...................................................... 369
EXDMAC Register Access during Operation ..................................................... 398
Module Stop State................................................................................................ 398
EDREQ Pin Falling Edge Activation................................................................... 398
Activation Source Acceptance ............................................................................. 399
Enabling Interrupt Requests when IRF = 1 in EDMDR ...................................... 399
ETEND Pin and CBR Refresh Cycle................................................................... 399
DTC Mode Register A (MRA) ............................................................................ 403
DTC Mode Register B (MRB)............................................................................. 404
DTC Source Address Register (SAR).................................................................. 405
DTC Destination Address Register (DAR).......................................................... 405
DTC Transfer Count Register A (CRA) .............................................................. 405
DTC Transfer Count Register B (CRB)............................................................... 405
DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 405
DTC Vector Register (DTVECR)........................................................................ 406
Normal Mode....................................................................................................... 412
Repeat Mode ........................................................................................................ 413
................................................................... 401
Rev. 3.00 Mar 17, 2006 page xix of l