HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 682

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 8-Bit Timers (TMR)
13.3.1
TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be
accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a
clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.
Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When
TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.
13.3.2
TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
The value in TCORA is continually compared with the value in TCNT. When a match is detected,
the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled
during the T2 state of a TCORA write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match A) and the settings of bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF.
13.3.3
TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during
the T2 state of a TCOBR write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF.
Rev. 3.00 Mar 17, 2006 page 630 of 926
REJ09B0283-0300
Timer Counter (TCNT)
Time Constant Register A (TCORA)
Time Constant Register B (TCORB)