HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 73

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
CPUS260A_020020020400
Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H object programs
General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
Sixty-nine basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Multiply-and-accumulate instruction
Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8
16 ÷ 8-bit register-register divide: 12 states
8-bit register-register multiply: 3 states
Features
Section 2 CPU
Rev. 3.00 Mar 17, 2006 page 21 of 926
REJ09B0283-0300
Section 2 CPU