HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 356
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 7 DMA Controller (DMAC)
7.5.7
In block transfer mode, data transfer is performed with channels A and B used in combination.
Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in
DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either
the transfer source or the transfer destination can be selected as a block area (an area composed of
a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
23
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
Rev. 3.00 Mar 17, 2006 page 304 of 926
REJ09B0283-0300
15
Block Transfer Mode
7
7
MARA
MARB
ETCRAH
ETCRAL
ETCRB
0
0
0
0
0
Function
Source address
register
Destination
address register
Holds block
size
Block size
counter
Block transfer
counter
Initial Setting
Start address of
transfer source
Start address of
transfer
destination
Block size
Block size
Number of block
transfers
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
Fixed
Decremented every
transfer; ETCRH value
copied when count
reaches H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000
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