HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 382

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
7.7
7.7.1
Except for forced termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
Rev. 3.00 Mar 17, 2006 page 330 of 926
REJ09B0283-0300
DMA Internal
address
DMA control
DMA register
operation
DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an
example of the update timing for DMAC registers in dual address transfer mode.
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
Usage Notes
DMAC Register Access during Operation
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Idle
[1]
Transfer
source
Read
Figure 7.39 DMAC Register Update Timing
DMA read
[2]
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Transfer
source
Read
[2']
DMA read
DMA last transfer cycle
destination
Write
Transfer
DMA write
[3]
Dead
DMA
dead
Idle