HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 198

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Bit
15
14
13
12
11
10
Rev. 3.00 Mar 17, 2006 page 146 of 926
REJ09B0283-0300
H8S/2678R Group
Bit Name
DRMI
—
TPC1
TPC0
SDWCD
—
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when
a continuous normal space access cycle follows
a DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
This bit can be read from or written to.
However, the write value should always be 0.
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tc1)
inserted by WTCR settings during synchronous
DRAM write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
Reserved
This bit can be read from or written to.
However, the write value should always be 0.