HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 773
HD64F2676VFC33
Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2676VFC33
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th
pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given
by the following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 –
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M = (0.5 – 1/2
= 49.866%
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
2N
1
186 clocks
0
372)
) – (L – 0.5) F –
(Using Clock of 372 Times the Bit Rate)
185
372 clocks
Start bit
100%
371
Section 15 Serial Communication Interface (SCI, IrDA)
D – 0.5
0
N
D0
(1 + F) × 100 [%]
Rev. 3.00 Mar 17, 2006 page 721 of 926
185
371 0
REJ09B0283-0300
D1
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