HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 391

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.3.2
EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
EDDAR value is ignored when a device with DACK is specified as the transfer destination. The
upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified.
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
8.3.3
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
Normal Transfer Mode:
Bit
31
to
24
23
to
0
Bit Name
—
EXDMA Destination Address Register (EDDAR)
EXDMA Transfer Count Register (EDTCR)
Initial Value
All 0
All 0
R/W
—
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
24-Bit Transfer Counter
These bits specify the number of transfers.
Setting H'000001 specifies one transfer. Setting
H'000000 means no specification for the
number of transfers, and the transfer counter
function is halted. In this case, there is no
transfer end interrupt by the transfer counter.
Setting H'FFFFFF specifies the maximum
number of transfers, that is 16,777,215. During
EXDMA transfer, this counter shows the
remaining number of transfers. This counter
can be read at all times. When reading EDTCR
for a channel on which EXDMA transfer
processing is in progress, a longword-size read
must be executed.
Rev. 3.00 Mar 17, 2006 page 339 of 926
Section 8 EXDMA Controller
REJ09B0283-0300