HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 400

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller
Bit
7
6
5
Rev. 3.00 Mar 17, 2006 page 348 of 926
REJ09B0283-0300
Bit Name
DAT1
DAT0
DARIE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Destination Address Update Mode
These bits specify incrementing/decrementing
of the transfer destination address (EDDAR).
When an external device with DACK is
designated as the transfer destination in single
address mode, the specification by these bits is
ignored.
0X: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in
Destination Address Repeat Interrupt Enable
When this bit is set to 1, in the event of
destination address repeat area overflow the
IRF bit is set to 1 and the EDA bit cleared to 0
in EDMDR, and transfer is terminated. If the
EDIE bit in EDMDR is 1 when the IRF bit in
EDMDR is set to 1, an interrupt request is sent
to the CPU. When used together with block
transfer mode, a destination address repeat
interrupt is requested at the end of a block-size
transfer. If the EDA bit is set to 1 in EDMDR for
the channel on which transfer is terminated by a
destination address repeat interrupt, transfer
can be resumed from the state in which it
ended. If a destination address repeat area has
not been designated, this bit is ignored.
0: Destination address repeat interrupt is not
1: When destination address repeat area
requested
overflow occurs, the IRF bit in EDMDR is set
to 1 and an interrupt is requested
transfer)
word transfer)