HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 48

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 9.4
Table 9.5
Table 9.6
Table 9.7
Section 10 I/O Ports
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10 TPSC2 to TPSC0 (Channel 5)................................................................................ 532
Table 11.11 MD3 to MD0.......................................................................................................... 534
Table 11.12 TIORH_0................................................................................................................ 536
Table 11.13 TIORL_0 ................................................................................................................ 537
Table 11.14 TIOR_1 .................................................................................................................. 538
Table 11.15 TIOR_2 .................................................................................................................. 539
Table 11.16 TIORH_3................................................................................................................ 540
Table 11.17 TIORL_3 ................................................................................................................ 541
Table 11.18 TIOR_4 .................................................................................................................. 542
Table 11.19 TIOR_5 .................................................................................................................. 543
Table 11.20 TIORH_0................................................................................................................ 544
Table 11.21 TIORL_0 ................................................................................................................ 545
Table 11.22 TIOR_1 .................................................................................................................. 546
Table 11.23 TIOR_2 .................................................................................................................. 547
Table 11.24 TIORH_3................................................................................................................ 548
Table 11.25 TIORL_3 ................................................................................................................ 549
Table 11.26 TIOR_4 .................................................................................................................. 550
Table 11.27 TIOR_5 .................................................................................................................. 551
Rev. 3.00 Mar 17, 2006 page xlvi of l
Input Pull-Up MOS States (Port A)........................................................................ 489
Input Pull-Up MOS States (Port B)........................................................................ 492
Input Pull-Up MOS States (Port C)........................................................................ 496
Input Pull-Up MOS States (Port D)........................................................................ 499
Input Pull-Up MOS States (Port E) ........................................................................ 503
Register Function in Repeat Mode ......................................................................... 413
Register Function in Block Transfer Mode ............................................................ 414
DTC Execution Status ............................................................................................ 418
Number of States Required for Each Execution Status .......................................... 419
Port Functions ........................................................................................................ 428
TPU Functions........................................................................................................ 522
Pin Configuration ................................................................................................... 525
CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 529
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 529
TPSC2 to TPSC0 (Channel 0)................................................................................ 530
TPSC2 to TPSC0 (Channel 1)................................................................................ 530
TPSC2 to TPSC0 (Channel 2)................................................................................ 531
TPSC2 to TPSC0 (Channel 3)................................................................................ 531
TPSC2 to TPSC0 (Channel 4)................................................................................ 532