ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 124

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Watchdog Timer Operation
System Clock
RTC Clock
Enabling and Disabling the Watchdog Timer
The WDT is disabled on a RESET. To enable the WDT, the application program must set
WDT_EN, which is bit 7 of the WDT_CTL register. After WDT_EN is set, no Writes are
allowed to the WDT_CTL register. When enabled, the WDT cannot be disabled except by
a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT. The WDT time-out period is
defined by the WDT_PERIOD WDT_CTL[1:0] field and WDT_CLK WDT_CTL[3:2]
field of the Watchdog Timer control register (WDT_CTL = 0093h). The approximate
time-out period and corresponding clock cycles for three different WDT clock sources are
listed in
The WDT time-out period divider is set to one of the four available settings for the
selected frequency of the WDT clock source. Basing the divider settings on the clock
source values provides a time-out range from few seconds to few milliseconds, regardless
of the frequency setting.
Oscillator
WDT
Table 47
WDT_CLK
Figure 25. Watchdog Timer Block Diagram
on page 117.
Time-out Compare Logic
(WDT_PERIOD)
Upcounter
28-Bit
RESET
NMI to eZ80 CPU
WDT Control Logic
Control Register/
Reset Register
Product Specification
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eZ80F91 ASSP
Watchdog Timer
116