ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 145
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ez80f91
Manufacturer Part Number
ez80f91
Description
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F91.pdf
(387 pages)
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PS027001-0707
Timer Data Register—High Byte
The Timer x Data Register—High Byte returns the High byte of the count value of the
selected timer as it existed at the time that the Low byte was read. The Timer Data
Register—High Byte (see
current count value does not affect timer operation. To read the 16-bit data of the
current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read the Timer Data
Register—Low Byte followed by the Timer Data Register—High Byte. The Timer Data
Register—High Byte value is latched into temporary storage when a Read of the Timer
Data Register—Low Byte occurs.
This register shares its address with the corresponding timer reload register.
Table 58. Timer Data Register—High Byte
0069h, TMR2_DR_H = 0073h, TMR3_DR_H = 0078h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR_DR_H
Value
00h–FFh
Table
Description
These bits represent the High byte of the 2-byte timer data
value, {TMR
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit
timer data value.
R
7
0
58) is read when the timer is in operation. Reading the
R
6
0
x
_DR_H[7:0], TMR
R
5
0
(TMR0_DR_H = 0064h, TMR1_DR_H =
R
4
0
x
_DR_L[7:0]}. Bit 7 is bit 15
R
3
0
Programmable Reload Timers
Product Specification
R
2
0
eZ80F91 ASSP
R
1
0
R
0
0
137
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