ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 190

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 94. UART Baud Rate Generator Register—Low Bytes
UART1_BRG_L = 00D0h)
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_L
Note:
BRG Control Registers
UART Baud Rate Generator Register—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by the CPU
for UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. Upon RESET, the 16-bit BRG divisor value resets to
16-bit divisor value must be between
0001h
the minimum BRG clock divisor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register. See
UART Line Control Register
The UARTx_BRG_L registers share the same address space with the UARTx_RBR and
UARTx_THR registers. The UARTx_BRG_H registers share the same address space with
the UARTx_IER registers. Bit 7 of the associated UART Line Control register
(UARTx_LCTL) must be set to 1 to enable access to the BRG registers.
Value
00h–FFh
are invalid and proper operation is not guaranteed at these two values. As a result,
R/W
7
0
Description
These bits represent the Low byte of the 16-bit BRG divider value. The
complete BRG divisor value is returned by {UART_BRG_H,
UART_BRG_L}.
R/W
Table 94
6
0
on page 188.
R/W
and
5
0
0002h
Table 95
R/W
4
0
and
on page 183. For more information, see
Universal Asynchronous Receiver/Transmitter
FFFFh
R/W
3
0
(UART0_BRG_L = 00C0h,
, because the values
R/W
2
0
Product Specification
0002h
R/W
1
1
eZ80F91 ASSP
. The initial
0000h
R/W
0
0
and
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