ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 164

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Pulse-Width Modulation Control Register 3
The PWM Control Register 3 (see
functionality.
Table 75. PWM Control Register 3
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read only.
Bit
Position
7
PT_IC3_EN
6
PT_IC2_EN
5
PT_IC1_EN
4
PT_IC0_EN
3
PT_TRI
2
PT_LVL
1
PT_LVL_N
0
PTD
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Power trip disabled on IC3.
Power trip enabled on IC3.
Power trip disabled on IC2.
Power trip enabled on IC2.
Power trip disabled on IC1.
Power trip enabled on IC1.
Power trip disabled on IC0.
Power trip enabled on IC0.
All PWM trip levels are open-drain
All PWM trip levels are defined by PT_LVL and PT_LVL_N
After power trip, PWMx outputs are set to one.
After power trip, PWMx outputs are set to zero.
After power trip, PWMx outputs are set to one.
After power trip, PWMx outputs are set to zero.
Power trip has been cleared.
This bit is set after power trip event.
R/W
7
0
R/W
Table
6
0
75) is used to configure the PWM power trip
(PWM_CTL3 = 007Bh)
R/W
5
0
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 ASSP
R/W
1
0
R
0
0
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