ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 140

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Timer Control Register
The Timer x Control Register (see
enabling the timer, selecting the clock source, selecting the clock divider, selecting
between CONTINUOUS and SINGLEPASS modes, and enabling the auto-reload
feature.
Table 54. Timer Control Register
TMR2_CTL = 006Fh, TMR3_CTL = 0074h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
BRK_STOP
[6:5]
CLK_SEL
[4:3]
CLK_DIV
2
TIM_CONT
Value
0
1
00
01
10
11
00
01
10
11
0
1
Timer source is the system clock divided by the prescaler.
System clock divider = 4.
System clock divider = 16.
System clock divider = 64.
Description
The timer continues to operate during debug break points.
The timer stops operation and holds count value during debug
break points.
Timer source is the Real Time Clock Input.
Timer source is the Event Count (ECx) input—falling edge.
For Timer 1 this is EC0.
For Timer 2, this is EC1.
Timer source is the Event Count (ECx) input—rising edge.
For Timer 1 this is EC0.
For Timer 2, this is EC1.
System clock divider = 256.
The timer operates in SINGLE PASS mode. TIM_EN (bit 0) is
reset to 0 and counting stops when the end-of-count value is
reached.
The timer operates in CONTINUOUS mode. The timer reload
value is written to the counter when the end-of-count value is
reached.
R/W
7
0
R/W
Table
6
0
(TMR0_CTL = 0060h, TMR1_CTL = 0065h,
54) is used to control timer operations including
R/W
5
0
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 ASSP
R/W
1
0
R/W
0
0
132