ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 360

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 239. External Memory Write Timing
PS027001-0707
Parameter
T
T
T
T
T
T
T
T
T
T
*At the conclusion of a Write cycle, deassertion of WR always occurs before any change to
ADDR, DATA, CSx, or MREQ.
1
2
3
4
5
6
7
8
9
10
Abbreviation
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
PHI Clock Fall to DATA Valid
PHI Clock Rise to DATA Hold Time
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to MREQ Assertion Delay
PHI Clock Rise to MREQ Deassertion Delay
PHI Clock Fall to WR Assertion Delay
PHI Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
WR Deassertion to DATA Hold Time
WR Deassertion to CSx Hold Time
WR Deassertion to MREQ Hold Time
Minimum
1.0
2.3
0.0
2.3
2.3
0.0
0.4
0.5
1.2
0.5
—
—
—
1
Delay (ns)
Maximum
10.8
8.5
2.5
6.0
7.0
6.5
1.0
5.0
—
—
—
—
—
—
Product Specification
Electrical Characteristics
eZ80F91 ASSP
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