ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 146
ez80f91
Manufacturer Part Number
ez80f91
Description
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F91.pdf
(387 pages)
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PS027001-0707
Timer Reload Register—Low Byte
The Timer x Reload Register—Low Byte (see
(LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is
reloaded into the timer on end-of-count. When the reload bit (TMRx_CTL[RLD]) is set to
1 forcing the reload function, the timer reload value is written to the timer on the next ris-
ing edge of the clock.
This register shares its address with the corresponding timer data register.
Table 59. Timer Reload Register—Low Byte
= 0068h, TMR2_RR_L = 0072h, TMR3_RR_L = 0077h)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
TMR_RR_L
Value
00h–FFh
W
7
0
Description
These bits represent the Low byte of the 2-byte timer
reload value, {TMR
is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of
the 16-bit timer reload value.
W
6
0
W
5
0
Table
x
_RR_H[7:0], TMR
(TMR0_RR_L = 0063h, TMR1_RR_L
W
4
0
59) stores the least-significant byte
W
3
0
Programmable Reload Timers
Product Specification
W
2
0
x
_RR_L[7:0]}. Bit 7
eZ80F91 ASSP
W
1
0
W
0
0
138
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