ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 214

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
SPI Functional Description
SPI Flags
When a master transmits to a slave device via the MOSI signal, the slave device responds
by sending data to the master via the master's MISO signal. The result is a full-duplex
transmission, with both data out and data in synchronized with the same clock signal. The
byte transmitted is replaced by the byte received, eliminating the need for separate trans-
mit-empty and receive-full status bits. A single status bit, SPIF, is used to signify that the
I/O operation is complete. See
The SPI is double-buffered during reads, but not during Writes. If a Write is performed
during data transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This
condition causes the write collision (WCOL) status bit in the SPI_SR register to be set.
After a data byte is shifted, the SPI flag of the SPI_SR register is set to 1.
In SPI MASTER mode, the SCK pin functions as an output. It idles High or Low depend-
ing on the CPOL bit in the SPI_CTL register until data is written to the shift register. Data
transfer is initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then
generated to shift the eight bits of transmit data out via the MOSI pin while shifting in
eight bits of data via the MISO pin. After transfer, the SCK signal becomes idle.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin; as a result, the slave is synchronized to the master. Data from the
master is received serially from the slave MOSI signal and is loaded into the 8-bit shift
register. After the 8-bit shift register is loaded, its data is parallel-transferred to the Read
buffer. During a Write cycle, data is written into the shift register. Next, the slave waits for
the SPI master to initiate a data transfer, supply a clock signal, and shift the data out on the
slave's MISO signal.
If the CPHA bit in the SPI_CTL register is 0, a transfer begins when the SS pin signal goes
Low. The transfer ends when SS goes High after eight clock cycles on SCK. When the
CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low.
The transfer ends when the SPI flag is set to 1.
Mode Fault
The Mode Fault flag (MODF) indicates that there is a multimaster conflict in the system
control. The MODF bit is normally cleared to 0 and is only set to 1 when the master
device’s SS pin is pulled Low. When a mode fault is detected, the following sequence
occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE
mode.
SPI Status Register
on page 211.
Product Specification
Serial Peripheral Interface
eZ80F91 ASSP
206