ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 234

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 124. I
Table 125. I
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
Bit
Reset
CPU Access
Note: R/W = Read/Write.
2
2
C Slave Address Register
C Extended Slave Address Register
When the register receives an address starting with
the I
ACK after receiving the I
point). After the next byte of the address (I
interrupt and enters SLAVE mode.Then I
10-bit extended address. The full 10-bit address is supplied by {I
I
I
The I
bit addressing of the I
bits of the 10-bit slave address. The full 10-bit address is supplied by {I
I
When the register receives an address starting with
the I
ACK after receiving the I
point). After the next byte of the address (I
interrupt and enters SLAVE mode.Then I
10-bit extended address. The full 10-bit address is supplied by {I
I
2
2
2
2
C_XSAR[7:0]}. See
C Extended Slave Address Register
C_XSAR[7:0]}.
C_XSAR[7:0]}. See
Value
00h–7Fh 7-bit slave address or upper 2 bits, I
0
1
2
2
2
C recognizes that a 10-bit slave addressing mode is being selected. The I
C recognizes that a 10-bit slave addressing mode is being selected. The I
C_XSAR register is used in conjunction with the I
R/W
R/W
7
0
7
0
Description
address when operating in 10-bit mode.
I
I
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
R/W
R/W
6
0
6
0
2
C when in SLAVE mode. The I
Table
Table 125
2
2
C_SAR byte (the device does not generate an interrupt at this
R/W
C_XSAR byte (the device does not generate an interrupt at this
R/W
5
0
5
0
(I2C_SAR = 00C8h)
124.
on page 226.
R/W
R/W
4
0
4
0
2
(I2C_XSAR = 00C9h)
2
C_SAR[2:1] are used as the upper 2 bits for the
C_SAR[2:1] are used as the upper 2 bits for the
2
R/W
2
R/W
C_XSAR) is received, the I
C_XSAR) is received, the I
3
0
3
0
2
F7h
R/W
C_SAR[2:1], of
F7h
R/W
2
0
2
0
2
C_SAR value forms the lower 8
to
to
2
C_SAR register to provide 10-
F0h
F0h
R/W
R/W
1
0
1
0
(I
(I
Product Specification
2
2
2
2
C_SAR[7:3] = 11110b),
C_SAR[7:3] = 11110b),
C_SAR[2:1],
C_SAR[2:1],
R/W
R/W
0
0
0
0
I
2
C Serial I/O Interface
2
2
2
C generates an
C generates an
eZ80F91 ASSP
C_SAR[2:1],
2
2
C sends an
C sends an
226