ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 86

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 23. Intel Bus Mode Read States—Multiplexed Address and Data Bus
Table 24. Intel Bus Mode Write States—Multiplexed Address and Data Bus
PS027001-0707
STATE T1
STATE T2
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
The Read cycle begins in State T1. The CPU drives the address onto the DATA bus and the
associated chip select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
During State T2, the CPU removes the address from the DATA bus and asserts the RD
signal. Depending upon the instruction, either the MREQ or IORQ signal is asserted.
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel™ bus mode cycle.
The Write cycle begins in State T1. The CPU drives the address onto the DATA bus and
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
During State T2, the CPU removes the address from the DATA bus and drives the Write
data onto the DATA bus. The WR signal is asserted to indicate a Write operation.
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write
operation. The CPU holds the data and address buses through the end of T4. The bus cycle
is completed at the end of T4.
WAIT
WAIT
Intel™ Bus Mode—Multiplexed Address and Data Bus
During Read operations with multiplexed address and data, the Intel™ bus mode employs
4 states—T1, T2, T3, and T4 as described in
During Write operations with multiplexed address and data, the Intel™ bus mode employs
4 states—T1, T2, T3, and T4 as described in
Signal timing for Intel bus mode with multiplexed address and data is illustrated for a
Read operation in
In
tem clock cycles in duration.
the assertion of one wait state (T
Figure 15
) are asserted until the READY pin is driven High.
) are asserted until the READY pin is driven High.
on page 79 and
Figure 15
on page 79 and for a Write operation in
Figure 16
Figure 15
WAIT
) by the selected peripheral.
on page 80, each Intel bus mode state is 2 CPU sys-
on page 79 and
Table
Table
23.
24.
Figure 16
Chip Selects and Wait States
Product Specification
on page 80 also illustrate
Figure 16
eZ80F91 ASSP
on page 80.
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