ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 148

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Timer Input Capture Value A Register—Low Byte
The Timer x Input Capture Value A Register—Low Byte (see
byte of the capture value for external input A. For Timer 1, the external input is IC0. For
Timer 3, it is IC2.
Table 62. Timer Input Capture Value Register A—Low Byte
006Bh, TMR3_CAPA_L = 007Ch)
[3:2]
CAP_EDGE_B
[1:0]
CAP_EDGE_A
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR
x
_CAPA_L
00
01
10
11
00
01
10
11
Value
00h–FFh
R
7
0
Disable capture on ICB.
Enable capture only on the falling edge of ICB.
Enable capture only on the rising edge of ICB.
Enable capture on both edges of ICB.
Disable capture on ICA.
Enable capture only on the falling edge of ICA
Enable capture only on the rising edge of ICA.
Enable capture on both edges of ICA.
Description
These bits represent the Low byte of the 2-byte capture
value, {TMR
bit 7 of the 16-bit data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
R
6
0
x
_CAPA_H[7:0], TMR
R
5
0
R
4
0
R
3
0
Table
Programmable Reload Timers
Product Specification
x
_CAPA_L[7:0]}. Bit 7 is
62) stores the Low
R
2
0
(TMR1_CAPA_L =
eZ80F91 ASSP
R
1
0
R
0
0
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