ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 341

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 221. EMAC Receive Write Pointer Register—High Byte
Table 222. EMAC Transmit Read Pointer Register—Low Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_RWP_H
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_TRP_L
EMAC Receive Write Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Receive Write Pointer Register are always zero.
EMAC Transmit Read Pointer Register—Low Byte
The Low byte of the Transmit Read Pointer register reports the current TxDMA Transmit
Read pointer.This pointer is initialized to EmacTLBP whenever Emac_RST bits SRST or
HRRTN are set. Because the size of the packet is limited to a minimum of 32 bytes, the
last five bits are always zero. See
Value
00h–E0h These bits represent the Low byte of the 2 byte EMAC
Value
00h–1Fh These bits represent the High byte of the 2 byte EMAC
R
R
7
0
7
0
Description
TxDMA
EMAC_TRP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.
Description
RxDMA Receive Write Pointer value, {EMAC_RWP_H,
EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.
R
R
6
0
6
0
Transmit Read Pointer
R
R
5
0
5
0
Table
R
R
4
0
4
0
222.
R
R
3
0
3
0
value, {EMAC_TRP_H,
R
R
2
0
2
0
(EMAC_RWP_H = 0052h)
(EMAC_TRP_L = 0053h)
Ethernet Media Access Controller
R
R
1
0
1
0
Product Specification
R
R
0
0
0
0
eZ80F91 ASSP
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