ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 126

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Table 48. Watchdog Timer Control Register
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
5
RST_FLAG
4
NMI_FLAG
[3:2]
WDT_CLK
Value Description
0
1
0
1
0
1
0
1
00
01
10
11
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be disabled
without a RESET.
WDT time-out resets the CPU.
WDT time-out generates a NMI to the CPU.
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, only if the NMI_OUT flag is set to 0. The CPU polls
this bit to determine the source of the RESET. This flag is
cleared by a non-WDT generated reset.
NMI caused by external source.
NMI caused by WDT time-out. This flag is set by the WDT time-
out, only if the NMI_OUT flag is set to 1. The CPU polls this bit
to determine the source of the NMI. This flag is cleared by a
non-WDT NMI.
WDT clock source is system clock.
WDT clock source is Real-Time Clock source (32 kHz on-chip
oscillator or 50/60 Hz input as set by RTC_CTRL[4]).
WDT clock source is internal RC oscillator (10 kHz typical).
Reserved
R/W
7
0
R/W
6
0
0/1
R
5
(WDT_CTL = 0093h)
R
4
0
R/W
3
1
Product Specification
R/W
2
0
eZ80F91 ASSP
Watchdog Timer
R/W
1
0
R/W
0
0
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