ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 212

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
SPI Signals
The four basic SPI signals are:
•
•
•
•
These SPI signals are discussed in the following paragraphs. Each signal is described in
both MASTER and SLAVE modes.
Master In, Slave Out
The Master In, Slave Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most-
significant bit sent first. The MISO pin of a slave device is placed in a high-impedance
state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master Out, Slave In
The Master Out, Slave In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the most-
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Slave Select
The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It
must be Low prior to all data communication and must stay Low for the duration of the
data transfer.
The SS input signal must be High for the SPI to operate as a master device. If the SS signal
goes Low in Master mode, a Mode Fault error flag (MODF) is set in the SPI_SR register.
For more information, see
When the clock phase (CPHA) is set to 0, the shift clock is the logical OR of SS with
SCK. In this clock phase mode, SS must go High between successive characters in an
SPI message. When CPHA is set to 1, SS remains Low for several SPI characters. In
cases where there is only one SPI slave, its SS line could be tied Low as long as CPHA
is set to 1. For more information on CPHA, see
Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device via its MOSI and MISO pins. The master and slave are each capable of exchanging
a byte of data during a sequence of eight clock cycles. Because SCK is generated by the
MISO (Master In, Slave Out)
MOSI (Master Out, Slave In)
SCK (SPI Serial Clock)
SS (Slave Select)
SPI Status Register
on page 211.
SPI Control Register
Product Specification
Serial Peripheral Interface
on page 210.
eZ80F91 ASSP
204