ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 59

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
GPIO Mode 3—Open Drain
The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an
internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode,
an external pull-up resistor must connect the pin to the supply voltage. Writing 0 to the
Port x Data register outputs a Low at the pin. Writing 1 to the Port x Data register results in
high-impedance output.
GPIO Mode 4—Open Source
The port pin is configured as open-source I/O. The GPIO pins do not feature an internal
pull-down to the supply ground. To employ the GPIO pin in OPEN-SOURCE mode, an
external pull-down resistor must connect the pin to the supply ground. Writing 1 to the
Port x Data register outputs a High at the pin. Writing 0 to the Port x Data register results
in a high-impedance output.
GPIO Mode 5
This mode produces a high-impedance output.
GPIO Mode 6
The port pin is configured for dual edge-triggered interrupt mode. Both a rising and a
falling edge on this pin cause an interrupt request to be sent to the CPU. To select this
mode from the default mode (mode 2), you must:
1. Set Px_DR=1
2. Set Px_ALT2=1
3. Set Px_ALT1=0
4. Set Px_DDR=0
Writing a 1 to the Port x ALT0 register bit position corresponding to the interrupt request
clears the interrupt.
GPIO Mode 7—Alternate Functions
The port pin is configured to pass control over to the alternate (secondary) functions
assigned to the pin. For example, the alternate mode function for PC5 is the DSR1 input
signal to UART1 and the alternate mode function for PB4 is the timer 3 input capture.
When GPIO mode 7 is enabled, the pin output data and pin high-impedance control is
obtained from the alternate function's data output and high-impedance control,
respectively. The value in the Port x Data register produces no effect on operation. Input
signals are sampled by the system clock before being passed to the alternate input
function.
If the alternate function of a pin is an input and alternate function mode for that pin is not
enabled, the input is driven to a default non-asserted value. For example, in alternate mode
—
—
Reserved
Dual Edge Triggered
General Purpose Input/Output
Product Specification
eZ80F91 ASSP
51