ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 219

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 115. SPI Status Register
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
SPI Status Register
The SPI Status Read Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data over
SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly into
the shift register for transmission. A Write to this register within an SPI device configured
as a master initiates transmission of the byte of the data loaded into the register. At the
completion of transmitting a byte of data, the SPI Flag (SPI_SR[7]) is set to 1 in both the
master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the SPI
Receive Buffer Read Only register. See
Value Description
0
1
0
1
0
0
1
0000
Table
115.
SPI data transfer is not finished.
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit Flag is cleared to 0
by a Read of the SPI_SR registers.
Reserved.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit Flag is
cleared to 0 by a Read of the SPI_SR register.
Reserved.
R
7
0
(SPI_SR = 00BBh)
R
6
0
R
5
0
R
4
0
Table 116
R
3
0
on page 212.
R
2
0
R
1
0
Product Specification
Serial Peripheral Interface
R
0
0
eZ80F91 ASSP
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