ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 213

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 111. SPI Clock Phase and Clock Polarity Operation
PS027001-0707
CPHA
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
0
0
1
1
ENABLE (To Slave)
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
Sample Input
CPOL
master, the SCK pin becomes an input on a slave device. The SPI contains an internal
divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half the fre-
quency of the clock signal created by the SPI’s Baud Rate Generator.
As demonstrated in
using the clock polarity (CPOL) and clock phase CPHA control bits in the SPI Control
register. See
with the identical timing, CPOL, and CPHA. The master device always places data on the
MOSI line a half-cycle before the clock edge (SCK signal), for the slave device to latch
the data.
0
1
0
1
Transmit
SPI Control Register
Falling
Falling
Rising
Rising
Edge
SCK
MSB
MSB
Figure 42
1
Figure 42. SPI Timing
SCK
Receive
Edge
6
Falling
Falling
Rising
Rising
6
2
and
Number of Cycles on the SCK Signal
5
on page 210. Both the master and slave must operate
Table
5
3
111, four possible timing relations are chosen by
4
State
SCK
High
High
Low
Low
Idle
4
4
3
3
5
Characters?
2
Between
SS High
Yes
Yes
No
No
2
6
Product Specification
1
Serial Peripheral Interface
1
7
eZ80F91 ASSP
LSB
LSB
8
205