ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 318

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 189. EMAC_IPGT Back-to-Back Settings for Full- and Half-Duplex Modes
PS027001-0707
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
Duplex
*12h
Half
Clock Period = 40 ns
MII, RMII/SMII, PMD
(100 Mbps)
Duplex
IPGT[6:0]
0Dh
0Ch
0Bh
10h
15h
20h
Full
The equations for back-to-back Transmit IPG are determined by the following:
Table 190
FULL-DUPLEX Mode (3 clocks + IPGT clocks) * clock period = IPG
HALF-DUPLEX Mode (6 clocks + IPGT clocks) * clock period = IPG
Interpacket
0.44 µs
0.60 µs
0.76 µs
0.96 µs
1.40 µs
0.12 µs
Gap
on page 311 lists the IPGR2 settings for the non-back-to-back packets.
Duplex
Half
12h
Clock Period = 400 ns
MII, RMII/SMII
(10 Mbps)
Duplex
IPGT[6:0]
0Ch
Full
00h
08h
10h
15h
20h
Interpacket
14.0 µs
1.2 µs
4.4 µs
6.0 µs
7.5 µs
9.6 µs
Gap
Duplex
Half
5Ah
Ethernet Media Access Controller
Clock Period = 100 ns
Product Specification
ENDEC Mode
(10 Mbps)
Duplex
IPGT[6:0]
5Dh
Full
10h
18h
20h
40h
20h
eZ80F91 ASSP
Interpacket
13.0 µs
1.9 µs
2.7 µs
3.5 µs
6.7 µs
9.6 µs
Gap
310