ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 246

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated
in
ZCL as illustrated in
the ninth cycle and holds the ZCL signal High.
ZDI Single-Bit Byte Separator
Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a
new ZDI command, the single-bit byte separator must be High (logical 1) to allow for a
new ZDI START command to be sent. For all other cases, the single-bit byte separator is
either Low (logical 0) or High (logical 1). When ZDI is configured to allow the CPU to
ZDA
ZCL
Figure
ZDA
ZCL
50. Data is shifted out during a Read from the ZDI block on the falling edge of
Start Signal
Start Signal
Figure
51. When an operation is completed, the master stops during
Figure 50. ZDI Write Timing
Figure 51. ZDI Read Timing
ZDI Data In
(Write)
ZDI Data Out
(Read)
ZDI Data In
(Write)
Product Specification
ZDI Data Out
(Read)
Zilog Debug Interface
eZ80F91 ASSP
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