ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 188

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
completed transmission. When the application makes this determination, it writes the
transmit data bytes to the UARTx_THR register. The number of bytes that the application
writes depends on whether or not the FIFO is enabled. If the FIFO is enabled, the applica-
tion writes 16 bytes at a time. If not, the application writes one byte at a time. As a result
of the first Write, the interrupt is deactivated. The CPU then waits for the next interrupt.
When the interrupt is raised by the UART module, the CPU repeats the same process until
it exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by writing to
the UARTx_MCTL register and reading the UARTx_MCTL register before starting the
process described above.
In RS485 multidrop mode, the first byte of the message is the station address and the rest
of the message contains the data for that station. You must set the Even Parity Select (EPS
bit 4) and Parity Enable (PEN bit 3) in the UARTx_LCTL before sending the station
address. We recommend that in your UART initialization routine set up the
UARTx_LCTL register for your data transfer format and set the Parity Enable (PEN bit 3)
bit. Each time you want to send a new message you must perform these three steps:
1. Since the UART automatically clears the Even Parity Select (EPS bit 4) bit in the
2. Set the Even Parity Select (EPS bit 4) bit in the UARTx_LCTL register being careful
3. Send the rest of the message. Write data to the UART Transmit Holding Register
In multidrop mode, during receiving start address marks, you will see a receive line inter-
rupt (INSTS bits[3:1]) in the IIR register. Read the LSR and check for receive errors only
and ignore any parity errors. The parity is only used for address marks in this multidrop
mode.
Receive—
RxD input signal. When an interrupt is raised by the UART module, the application reads
the UARTx_IIR register and determines the cause for the interrupt. If the cause is a line
status interrupt, the application reads the UARTx_LSR register, reads the data byte and
then discards the byte or take other appropriate action. If the interrupt is caused by a
receive-data-ready condition, the application alternately reads the UARTx_LSR and
UARTx_RBR registers and removes all of the received data bytes. It reads the
UARTx_LCTL after a byte is sent, before starting a new message you have to wait for
the transmitter to go idle. The Transmit Empty (TEMT bit 6) of the UARTx_LSR will
be set. If you set the EPS bit of the UARTx_LCTL before the last byte of the previous
message is transmitted, the EPS bit will be cleared and the new station address will be
sent as data instead of being used as an address.
not to alter the other bits in the register sets the address mark. Write station address to
the UARTx_THR. The UART will automatically clear the EPS bit after the station
address byte is transmitted.
UARTx_THR whenever the Transmit Holding Register Empty (THRE bit 5) in the
UARTx_LSR is set.
The receiver is always enabled, and it continually checks for the start bit on the
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F91 ASSP
180