ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 320

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 192. EMAC Non-Back-To-Back IPG Register—Part 1
PS027001-0707
Bit
Position
7
[6:0]
IPGT
Bit
Reset
CPU Access
Note: R/W = Read/Write
Bit
Position
7
[6:0]
IPGR 1
EMAC Non-Back-To-Back IPG Register—Part 1
Part 1 of the EMAC non-back-to-back IPG Register is a programmable field representing
the optional carrier sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier Deference. If
a carrier is detected during the timing of IPGR1, the EMAC defers to the carrier. If, how-
ever, the carrier becomes active after IPGR1, the EMAC continues timing for IPGR2 and
transmits, knowingly causing a collision. This collision acts to ensure fair access to the
medium. Its range of values is
represents the Carrier Sense Window Referencing depicted tin IEEE 802.3, Section
4.2.3.2.1.
EMAC Non-Back-To-Back IPG Register—Part 2
Part 2 of the EMAC non-back-to-back IPG Register is a programmable field representing
the non-back-to-back IPG. Its default is
µs at 100 Mbps or 9.6 µs at 10 Mbps. See
Value
0
00h–7Fh The number of bytes of IPG.
Value
0
00h–
7Fh
R/W
Description
Reserved.
This is a programmable field representing the optional carrier
sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier
Deference.
Description
Reserved.
7
0
R/W
6
0
R/W
5
0
00h
R/W
to IPGR2. See
4
0
12h
R/W
Table 193
, which represents the minimum IPG of 0.96
3
1
Table
R/W
(EMAC_IPGR1 = 002Eh)
2
1
on page 313.
192. The default setting of 0Ch
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
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