ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 49

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Reset
PS027001-0707
Note:
External Reset Input and Indicator
The Reset controller within the eZ80F91 device features a consistent reset function for all
types of resets that affects the system. A system reset, referred in this document as RESET,
returns the eZ80F91 to a defined state. All internal registers affected by a RESET return to
their default conditions. RESET configures the GPIO port pins as inputs and clears the
CPU’s Program Counter to
The events that cause a RESET are:
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•
•
•
•
•
During RESET, an internal RESET mode timer holds the system in RESET for 1025
system clock (SCLK) cycles to allow sufficient time for the primary crystal oscillator to
stabilize. For internal RESET sources, the RESET mode timer begins incrementing on the
next rising edge of SCLK following deactivation of the signal that is initiating the RESET
event. For external RESET pin assertion, the RESET mode timer begins on the next rising
edge of SCLK following assertion of the RESET pin for three consecutive SCLK cycles.
The default clock source for SCLK on RESET is the crystal input (X
CLK_MUX values in the PLL Control Register 0, (see
The eZ80F91 RESET pin functions as both open-drain (active Low) RESET mode indica-
tor and active Low RESET input. When a RESET event occurs, the internal circuitry
begins driving the RESET pin Low. The RESET pin is held Low by the internal circuitry
until the internal RESET mode timer times out. If the external reset signal is released prior
to the end of the 1025 count time-out, program execution begins following the RESET
mode time-out. If the external reset signal is released after the end of the 1025 count time-
out, then program execution begins following release of the RESET input (the RESET pin
is High for four consecutive SCLK cycles).
Power-on reset (POR).
Low-Voltage Brownout (VBO).
External RESET pin assertion.
Watchdog Timer (WDT) time-out when configured to generate a RESET.
Real-Time Clock alarm with the CPU in low-power SLEEP mode.
Execution of a Debug RESET command.
000000h
. Program code execution ceases during RESET.
Table 154
Product Specification
on page 273).
IN
). See the
eZ80F91 ASSP
Reset
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